(1) Field of the Invention
The present invention relates to split-gate memory cells used in flash EEPROMs (Electrically Erasable Programmable Read Only Memories), and in particular, to a method of forming a tiny silicon nitride spacer by using a judicious combination of dry and wet etch in order to provide a better process window.
(2) Description of the Related Art
Silicon nitride spacer technology is widely used in split gate non-volatile memory cells such as flash EPROMs. A tiny spacer structure is formed on tunnel oxide layer adjacent to the sidewall of floating gate electrode to prevent write disturbance that is caused by reverse tunneling. The nitride spacer is usually performed by anisotropic dry etching. However, it is difficult to control and maintain the etch rate and uniformity in dry etching because the process window of spacer etching is very narrow, namely, about 3 seconds for forming and shaping a tiny spacer, which may be no larger than 250 angstroms (xc3x85) in height. Such a short etch time and the nonuniformity in the nitride film itself makes it very difficult to form tiny nitride spacers of controlled dimensions. A poorly defined spacer will cause, what is known in the art as xe2x80x9cwrite disturbxe2x80x9d, or, unwanted reverse tunneling, or erasing. Also, the endurance (the number of times the cell can be written and erased) is degraded as well as the erase and program (writing) speed of the cell. It is disclosed later in the embodiments of the present invention a method of opening up the etching process window from tens of seconds to several minutes with the attendant result of having much better controlled tiny silicon nitride spacers, and hence improved flash EPROM.
Most conventional flash-EEPROM cells use a double-polysilicon (poly) structure of which the well-known split-gate cell is shown in FIG. 1. There, a MOS transistor is formed on a semiconductor substrate (10) having a first doped region (11), a second doped region (13), a channel region (15), a gate oxide. (30), a floating gate (40), intergate dielectric layer (50) and control gate (60). Substrate (10) and channel region (15) have a first conductivity type, and the first (11) and second (13) doped regions have a second conductivity type that is opposite the first conductivity type.
As seen in FIG. 1, the first doped region, (11), lies within the substrate. The second doped region, (13), lies within substrate (10) and is spaced apart form the first doped region (11). Channel region (15) lies within substrate (10) and between first (11) and second (13) doped regions. Gate oxide layer (30) overlies substrate (10). Floating gate (40), to which there is no direct electrical connection, and which overlies substrate (10), is separated from substrate (10) by a thin layer of gate oxide (30) while control gate (60), to which there is direct electrical connection, is generally positioned over the floating gate with intergate oxide (50) therebetween.
The programming and erasing of an EEPROM is accomplished electrically and in-circuit by using Fowler-Nordheim (F-N) tunneling as is well known in prior art. Basically, a sufficiently high voltage is applied to the control gate and source while the drain is providing a constant flow of electrons in the channel region in the substrate. Some of these electrons gain enough energy to transfer from the substrate to the floating gate through the thin gate oxide layer by means of Fowler-Nordheim tunneling. The tunneling is achieved by raising the voltage level on the source to a sufficiently high value of about 12 volts so that the floating gate will couple at about 8 volts. As the electronic charge builds up on the floating gate, the electric field is reduced, which reduces the electron flow. When, finally, the high voltage is removed, the floating gate remains charged to a value lower than the threshold voltage of a logic high that would turn it off. Since tunneling process is reversible, the floating gate can be erased by raising the control gate voltage and grounding the drain and source, thereby causing the stored charge on the floating gate to flow to the control gate by Fowler-Nordheim tunneling. Of importance in the tunneling region are the quality and the thinness of the tunneling oxide separating the floating gate from the substrate. Inadvertent reverse tunneling, or erasure, for example, may occur if the tunnel oxide is degraded, or the spacer formed between the floating gate and the control gate is poorly shaped.
In prior art, spacers are formed in various, different ways. Chien, et al., in U.S. Pat. No. 5,879,993 form a spacer structure adjacent to the sidewall of a floating gate electrode with a top surface and sidewalls, the floating gate electrode being formed on a silicon oxide dielectric layer, and the silicon oxide dielectric layer being formed on the top surface of a semiconductor substrate. The method includes the following steps: form a cap layer on the floating gate electrode, and a blanket tunnel oxide on the device; forming an inner dielectric, spacer layer over the device including the cap layer and the sidewalls thereby with conforming sidewalls, and an outer dielectric, spacer layer over the inner dielectric, spacer layer including the conforming sidewalls; etching partially the outer dielectric, spacer layer with a dry etch to form an outer dielectric spacer adjacent to the conforming sidewalls; partially etching more of the outer dielectric, spacer layer with a wet etch to expose a portion of the conforming sidewalls of the inner dielectric, spacer layer; etching the portion of the inner dielectric, spacer layer unprotected by the outer dielectric spacer before forming interelectrode dielectric layers and the control gate electrode.
Another method of forming spacers for flash EEPROM devices is disclosed by Chien, et al., in U.S. Pat. No. 6,001,690. A silicon nitride layer is formed over the floating gate in a memory cell. In one embodiment, a full isotropic/anisotropic etching of a particular recipe is performed on the nitride layer, while in a second embodiment a partial isotropic/anisotropic etching is followed by full anisotropic etching, using a different recipe.
In still another U.S. Pat. No. 6,069,042, Chien, et al., teach a method for forming a multi-layer spacer (MLS) for flash EPROM devices. A composite tetraethylorthosilicate-silicon nitride (TEOS/Si3N4) layer is deposited over the floating gate and anisotropically etched to form the MLS.
On the other hand, Lin, et al., provide a method for forming a split-gate flash memory cell in U.S. Pat. No. 6,046,086, where an extra thin nitride layer is formed over the primary gate oxide layer, while Ogura, in U.S. Pat. No. 6,074,914, teaches a method of fabricating an electrically programmable read only memory device, which consists of a control/word gate and a floating gate on the side wall of the control gate.
It is disclosed in the present invention a different method of forming a spacer in a split-gate flash memory cell by judiciously combining dry etch with wet etch.
It is therefore an object of this invention to provide method of forming very small silicon nitride spacers in split-gate flash EPROM cells in order to prevent the occurrence of xe2x80x9cwrite disturbxe2x80x9d, unwanted reverse tunneling, or erasing.
It is another object of this invention to provide a method of forming small nitride spacers with well-controlled dimensions and well-defined shapes through a judicious combination of dry+wet over etch technique.
It is still another object of the present invention to provide a method where the process window is big enough to easily control the dimension and shape of the very small silicon nitride spacers that are useful in split gate flash memory cells.
It is yet another object of the present invention to provide a method of forming tiny silicon nitride spacers with an improved product turn around time by combining the etching of the tiny spacers with the step of removing the photomask after the performing of the voltage threshold implant.
These objects are accomplished by providing a substrate having a plurality of active and field regions defined; forming a gate oxide layer over said substrate; forming a first polysilicon layer over said gate oxide layer; forming a nitride hard mask layer over said first polysilicon layer; etching the nitride hard mask layer to define floating gate area; forming a poly oxide layer over said floating gate structure; etching said first polysilicon layer to define a floating gate structure using the poly oxide hard mask; forming a tunnel oxide layer over said substrate, including over said polyoxide layer; forming a silicon nitride layer over said tunnel oxide layer; performing a dry etch of said silicon nitride (SiN) layer to form first SiN spacers along the vertical sidewalls of said floating gate structure; performing a wet over-etch of said first SiN spacers to form tiny second SiN spacers along the vertical sidewalls of said floating gate structure; forming a voltage threshold (VT)-implant photomask over said substrate; performing a VT-implant; removing said VT-implant photomask; forming a low voltage threshold (VTE)-implant photomask; performing a VTE-implant; removing said VTE-implant photomask; forming an intergate oxide layer over said floating gate; forming a second polysilicon layer over said poly oxide layer; and etching said second polysilicon layer to form a control gate over said intergate poly oxide layer.
These objects are further accomplished in a second embodiment providing a substrate having a polysilicon floating gate and a polyoxide formed thereon; forming tunnel oxide over said substrate, including over said polyoxide layer; forming a silicon nitride (SiN) layer over said substrate, including over said polyoxide layer; dry etching said SiN layer to form first SiN spacers along the vertical sidewalls of said floating gate; forming a voltage threshold (VT)-implant photomask over said substrate; performing a VT-implant; performing wet etch to remove said VT-implant photomask and continuing to wet over-etch said SiN spacers to form tiny second SiN spacers; forming a low voltage threshold (VTE)-implant photomask; performing a VTE-implant; removing said VTE-implant photomask; forming an intergate oxide layer over said floating gate; forming a second polysilicon layer over said poly oxide layer; and etching said second polysilicon layer to form a control gate over said intergate poly oxide layer.